1. Technical Field
Embodiments of the invention relate to array capacitors for electronic packages, and more particularly to methods of fabricating an array capacitor.
2. Description of Related Art
Fabrication of thick array capacitors, e.g. having a thickness of about 1000 μm and above, has been fraught with difficulties. One reason is the high propensity to form tapered via holes due to limitations of current hole-drilling methods. Other disadvantages of having tapered vias, and voids in the via structures include increased mechanical stress to the via structures and undesirable variations in Equivalent Series Resistance and Equivalent Series Inductance of an array capacitor. Due to tapering of the via holes, voids are formed upon filling the via holes. These voids are undesirable as they constrict electrical current flow and thereby increase electrical resistance of the via structures.
Several fabrication methods have been devised in attempts to overcome the above problems associated with having tapered via structures, but have been unsatisfactory. One method of fabricating array capacitors having a thickness of about 1000 μm involves fabricating two blocks of array capacitors before the capacitor blocks are aligned and laminated together to form an array capacitor of increased thickness. More particularly, blocks of array capacitors, with about half the final required thickness, are subject to laser drilling to form via holes extending through the blocks. An appropriate fill material is then filled or plugged in the via holes to form the via structures. The blocks, together with the via structures, are then aligned and laminated together to form a combined array capacitor having increased thickness. There are, however, several drawbacks with this method. For example, aligning the capacitor blocks is time-consuming and yet imprecise, resulting in misalignment of the via structures at the adjoining surfaces. The combined array capacitor is also prone to delamination at the adjoining surfaces of the capacitor blocks. Further, overall capacitance density of the combined array capacitor is reduced as compared to another array capacitor of similar thickness but being formed from a single block. The reduction in overall capacitance density is due to loss of active electrode layers near the adjoining surfaces. Yet further, due to misalignment of the via holes, voids may be formed during filling of the via holes. These voids are undesirable as they constrict flow of electrical current and thereby increase electrical resistance of the via structures.